The present invention relates generally to computer bus architecture. More particularly, the invention relates to circuitry for interconnecting VMEbus and IBM PC/XT and AT bus architectures.
The VMEbus is a standard bus architecture which has become popular in automated manufacturing and processing environments. The VMEbus specification is defined in "VMEbus Specification Manual," Revision c.1, VMEbus International Trade Association, published by Printex Publishing, Inc., which is incorporated herein by reference.
The IBM PC/XT and the IBM AT bus architecture has become a popular industry standard in office automation, database management and in the display of graphical information. The IBM PC/XT architecture is described in IBM Technical Reference for the PC/XT, available from International Business Machines and the IBM AT architecture is described in IBM Technical Reference for the AT, available from International Business Machines both references are incorporated herein by reference. The IBM AT bus architecture may be considered as a superset of the IBM PC/XT architecture. The IBM AT bus architecture retains compatibility with IBM PC/XT architecture, adding additional features and capabilities. For convenience, unless otherwise designated, the term IBM AT architecture will be used to refer to both the IBM PC/XT architecture and the IBM AT architecture.
The VMEbus and the AT bus architectures each have their own strengths and weaknesses and there are numerous applications where it would be advantageous to utilize both architectures together to take advantage of collective strengths and minimize the weaknesses. For example, a manufacturing installation might use a VMEbus-based computer system to control manufacturing equipment in the harsh manufacturing environment. VMEbus computer systems are ideally suited for such applications. However, VMEbus computer systems do not enjoy the wealth of user-friendly database management, spreadsheet and visual display software available for IBM AT bus systems. The VMEbus-based manufacturing installation, without access to IBM AT software, would require extensive programming in order to duplicate the database, spreadsheet and visual display functions.
As another example, consider a scientific data analysis installation in which IBM AT bus-based computer systems collect real time data and process that data using a sophisticated statistical processing software package. Although well-suited at running sophisticated statistical processing software, the AT bus architecture is not as well suited at data collection, particularly in harsh environments.
An additional problem in uniting the VMEbus and AT bus architectures is the manner in which the processor of an AT system and the processor of a VMEbus device store information. The AT systems are based on an Intel processor which stores the most significant byte of a word or longword at the highest memory address and the least significant byte at the lowest memory address. VMEbus systems, however, incorporate a Motorola processor which stores the bytes of a word or longword in the opposite fashion: the most significant byte is stored at the lowest memory address and the least significant byte at the highest memory address. Accordingly, when data is passed between the Intel processor of an AT system and a Motorola processor of a VMEbus device, the bytes of the word being transferred must be reordered, or "swapped", for proper communication to occur.
The above discussion demonstrates the need for combining and uniting the VMEbus and AT bus architectures, to allow the user access to both the rugged and powerful VMEbus and the rich software environment of the IBM AT. The present invention provides such a solution in the form of an interface system between the VMEbus and the AT bus. In the preferred embodiments, the invention is implemented on a first circuit board which is configured to plug into the standard VME backplane thereby communicating with the VMEbus architecture. The first circuit board also implements a fully functional AT bus, complete with central processing unit and random access memory. A second circuit board, attachable to the first circuit board, and also adapted for attaching to the VMEbus backplane interfaces with the AT bus and provides additional AT computer functions such as input/output with disk drives and video displays.
The circuit of the invention allows the on-board central processing unit to act both as a fully functional master and slave on the VMEbus. The on-board random access memory is dual access and can be addressed by either the VMEbus as VMEbus memory or by the on-board central processing unit of the AT system as AT bus memory.
When the on-board central processing unit (an Intel 80286 or 80386 processor) is in the real mode, the on-board central processing unit communicates with the VMEbus through a programmable window which can be user-selected to address several different VMEbus addressing modes. When the central processing unit is in the protected mode, the central processing unit addresses the VMEbus by addressing portions of the on-board random access memory which maps directly into the VMEbus address space.
In addition to implementing a fully functional AT computer with fully functional AT bus, the invention provides additional features not found on a conventional AT computer, including additional maskable and nonmaskable interrupts, a watchdog timer circuit, a cache memory and cache controller, a bus snoop for detecting accesses to the dual access RAM, software abort and reset capability, as well as full access to the VMEbus and all VMEbus interrupt signals. Inherent incompatibilities between the Intel central processing unit architecture (IBM AT) and the Motorola architecture (VMEbus) are overcome by a mapping technique wherein certain read and/or write cycles of certain predefined memory locations are interpreted by the hardware as constituting signals or functions not commonly provided in both architectures.
To overcome the byte ordering problems encountered when passing data between the Intel processor of the AT computer and the Motorola processor of a VMEbus device, a byte "swapping" circuit is provided. The circuit generally includes a plurality of independent groups of buffers which are operable to selectively reorder the bytes of a word or longword to enable proper communication between the Intel and Motorola processors. The byte swapping circuit of the present invention is further operable to enable the bytes of a word or longword to be transmitted between the Intel processor of the present invention and a Motorola-based processor device operating on the VMEbus. In this mariner, the bytes of a word or longword may be appropriately reordered when necessary (i.e., when passing data between an Intel and a Motorola processor), as well as transmitted between an AT bus and a VMEbus without being altered.
For a more complete understanding of the invention, its objects and advantages, reference may be had to the following specification and to the accompanying drawings.